L64105 LSI Logic Corporation, L64105 Datasheet - Page 56

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 3.4
3-14
(Sheet 1 of 3)
(Dec)
Addr
192
193
194
195
196
197
198
199
200
(Hex)
Addr
C0
C1
C2
C3
C4
C5
C6
C7
C8
Memory Interface Registers
Bit(s)
2:1
5:4
7:0
7:0
7:0
7:0
2:0
7:3
7:0
7:0
0
1
2
3
4
5
6
7
0
3
6
7
Register Summary
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
R
R
Default
Value
(Hex)
00
00
00
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Status/Command/Data
Host Read FIFO Empty
Host Read FIFO Full
Host Write FIFO Empty
Host Write FIFO Full
DMA Read FIFO Empty
DMA Read FIFO Full
DMA Write FIFO Empty
DMA Write FIFO Full
Reserved
DMA Mode [1:0] (idle, DMA, R/W, block move)
Host SDRAM Transfer Byte Ordering
Refresh Extend [1:0]
DMA SDRAM Transfer Byte Ordering
Reserved
Host SDRAM Read Data [7:0]
Host SDRAM Write Data [7:0]
Host SDRAM Target Address [7:0]
Host SDRAM Target Address [15:8]
Host SDRAM Target Address [18:16]
Reserved
Host SDRAM Source Address [7:0]
Host SDRAM Source Address [15:8]
Page
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4-39
4-40
4-41
4-41
4-42
4-42
Ref.