L64105 LSI Logic Corporation, L64105 Datasheet - Page 150

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.102 Registers 285–288 (0x11D–0x120) Display Override Luma/Chroma Frame
Figure 4.103 Register 289 (0x121)
4-68
Reg. 285
Reg. 286
Reg. 287
Reg. 288
Reserved
MSB
MSB
LSB
LSB
7
Store Start Addresses [15:0]
7
6
CrCb 2’s Complement
VSYNC Input Type
Reserved
The host can write to these registers to override the display picture luma
and chroma frame store start addresses when the Display Override
Mode (Register 265, bits 4 and 5,
First Field Only (0b10).
Reserved
Register Descriptions
Display Override Chroma Frame Store Start Address [15:8]
Display Override Chroma Frame Store Start Address [7:0]
Display Override Luma Frame Store Start Address [15:8]
Display Override Luma Frame Store Start Address [7:0]
Number of Segments in RMM [5:0]
When this bit is set, the chroma components are
converted to 2’s-complement values with the centers at 0
instead of 128. This is done by effectively inverting the
MSB of the Cr and Cb values.
When this bit is set, the Vertical Sync pulse is an
Even/Not Odd field input. When this bit is cleared, the
Vertical Sync input is a pulse.
Clear this bit when writing to this register.
Clear this bit when writing to this register.
R/W
R/W
R/W
R/W
page
4-59) is set to Frame (0b01) or
1
Reserved
R/W 5
R/W 6
0
0
7
0