L64105 LSI Logic Corporation, L64105 Datasheet - Page 269

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

As soon as the Video Decoder acknowledges the Decode Start
Command, it starts parsing the payload data in the Video ES Channel
Buffer and sets the Decode Status Interrupt bit in Register 0
(page
4-2).
This causes the INTRn signal to the host to be asserted if it is not
masked for this interrupt. The host should then read the interrupt
registers to determine the cause of the interrupt.
The host can stop the Video Decoder by issuing a Decode Stop
Command (clearing bit 0 in Register 246). The Video Decoder, however,
completes reconstruction of the current picture before acknowledging the
command, i.e., it stops at the next picture boundary and generates the
Decode Status Interrupt. When the Video Decoder stops, the Display
Controller freezes on the last field of the currently displayed picture.
Note:
A channel stop also causes a Video Decoder stop.
As mentioned previously, the decode/reconstruction process runs in lock
step with the display. This ensures that the reconstruction of pictures
happens at the same rate as the display (30 frames/second for NTSC
and 25 frames/second for PAL) and results in the minimum amount of
memory for frame stores.
Figure 8.2
and
Figure 8.3
illustrate the process starting from channel
start, searching for the first sequence start code, through start of decode,
and then show the timing relationship between the reconstruction and the
display of pictures.
The host can follow the sequence by reading the First Slice Start Code
Detect Interrupt bit, Picture Start Code Detect Interrupt bit, and Begin
Active Video (BAV) Interrupt bit as the interrupts occur. These bits are in
Registers 0 and 1.
When a picture is encoded as two field pictures, there are two sets of
picture start codes and first slice start codes as shown in
Figure
8.3.
Video Decoder Pacing
8-27