L64105 LSI Logic Corporation, L64105 Datasheet - Page 236

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 7.3
7-8
Channel Buffer
Video ES Channel Buffer
Audio ES Channel Buffer
Video PES Header
Audio PES Header/System
Channel Buffer
Channel Buffer Architectures
The third item requiring additional channel buffering is caused by the use
of a slave mode pixel interface to the NTSC/PAL encoder. In this system
configuration, the decoder is locked to the external VSYNC and cannot
start decoding at a channel start until the next VSYNC arrives. This
results in a decode start delay of up to one field time or 20 ms in a PAL
system. The additional space required is then 20 ms x 15 Mbps =
300,000 bits (37,500 bytes). Although audio decoding starts immediately,
the audio must be delayed 20 ms to maintain A/V synchronization.
It is the host’s responsibility to program the start and end SDRAM
address for all the channel buffers, the video frame stores, and the OSD
regions. The registers listed in
the channel space in the L64105.
Memory Interface
Note:
Address Bits Start Address Registers End Address Registers
[7:0]
[13:8]
[7:0]
[13:8]
[7:0]
[13:8]
[7:0]
[13:8]
All channel buffer start and end addresses are 14 bits. The
SDRAM is addressed by the host and the L64105’s internal
microcontroller as if it were simple RAM. The start and end
addresses are the upper 14 bits. Therefore, buffer sizes are
specified in blocks of 128, 16-bit words or 256 bytes.
72
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77
80
81
88
89
(page
(page
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(page
Table 7.3
4-22)
4-23)
4-24)
4-25)
are used by the host to program
74
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78
79
82
83
90
91
(page
(page
(page
(page
4-23)
4-24)
4-24)
4-25)