L64105 LSI Logic Corporation, L64105 Datasheet - Page 375

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 11.6
1. Tc = 1/27 MHz = 37 ns.
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Description
Addr setup to ASn falling
Addr hold from ASn falling
ASn low pulse width
Data setup to DSn rising (Wr cycle)
Data hold from DSn rising (Wr cycle)
READ setup to DSn falling
READ hold from DSn falling
CSn setup to DSn falling
CSn hold from DSn rising
DSn low pulse width (Write Cycle)
DSn rising to DSn rising (Write Cycle)
CSn falling to WAITn/DTACKn active
DSn falling to WAITn low/DTACKn high
CSn rising to WAITn/DTACKn 3-state
DSn falling to WAITn high/DTACKn low (Write cycle)
DSn rising to WAITn low/DTACKn high
DSn low pulse width (Read Cycle)
DSn falling to DSn falling (Read Cycle)
DSn falling to WAITn high/DTACKn low (Read cycle)
Data setup BEFORE WAITn high/DTACKn low
(Read Cycle)
DSn falling to Data 3-state (Read Cycle)
READ falling to Data 3-state (Read Cycle)
Host Interface AC Timing (Motorola Mode)
AC Timing
0.5 Tc
3.5 Tc
4.5 Tc
3 Tc
4 Tc
Min
10
10
7
7
0
7
7
7
0
–
–
2
–
–
–
2
2
1
1
1
1
1
2.5 Tc
3.5 Tc
Max
12
12
15
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
+ 15
+ 15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11-9