L64105 LSI Logic Corporation, L64105 Datasheet - Page 127

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.62
Figure 4.63
Reg. 207
Reg. 208
Reg. 209
Reg. 210
Reg. 211
Reg. 212
MSB
MSB
MSB
Internal Phase State
LSB
LSB
LSB
(current cycle) [1:0]
7
Read Only
Register 206 (0x0CE)
Registers 207–212 (0x0CF–0x0D4)
7
6
Internal SDRAM State [2:0]
Reserved
When the two internal clocks reach synchronization, the internal phase
state should be looping through states 01, 10, and 11. If a 00 state is
ever reached, it indicates that the synchronization has been lost. These
registers are used for diagnostic purposes only.
Memory Interface Registers
Internal Phase State
(1 cycle before) [1:0]
5
Read Only
Used to monitor the internal SDRAM state (diagnostics
only).
Bits [5:3]
0b000
0b001
0b010
0b011
0b100
0b101
Phase Detect Test High Freq [15:8]
Phase Detect Test Low Freq [15:8]
Phase Detect Test High Freq [7:0]
Phase Detect Test Low Freq [7:0]
4
VCO Test High Freq [15:8]
VCO Test High Freq [7:0]
(2 cycles before) [1:0]
Internal Phase State
R/W
R/W
R/W
R/W
R/W
R/W
Description
Waiting for 2 clocks to reach synchronization
SDRAM initialization (precharge both banks)
SDRAM Initialization (first 8 refreshes)
SDRAM Initialization (set mode register)
SDRAM Initialization (second 8 refreshes)
SDRAM ready to operate
3
Read Only
2
(3 cycles before) [1:0]
Internal Phase State
1
Read Only
R [5:3]
0
0
[7:6]
4-45