L64105 LSI Logic Corporation, L64105 Datasheet - Page 144

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.92
4-62
Bottom Field
Top/Not
7
Even Field
Odd/Not
Register 275 (0x113)
6
Freeze Mode [1:0]
3:2 Pulldown from Bitstream
Host Repeat First Field
Host Top Field First
First Field
Register Descriptions
First Field
5
These bits select the Freeze Mode according to the
following table.
Freeze Mode
0b00
0b01
0b10
0b11
Setting this bit causes the L64105 to decode pulldown
control from the MPEG-2 syntax in the bitstream.
Clearing this bit allows the host to control pulldown. The
default value for this bit is 1 (at power-up or chip reset).
When this bit is set, the first displayed field in a frame is
repeated during the third field time. This is the primary
mechanism for performing 3:2 pulldown from the host
interface. The default value for this register is 0.
When this bit is set, the first displayed field in a frame is
the top field (or odd field lines). This bit is used in
conjunction with the Host Repeat First Field for
controlling 3:2 pulldown. The default value for this register
is 1.
This bit is set to indicate that the current field being
displayed is the first field of the frame and cleared when
it is the last field. Normally, this bit and the Last Field bit
in the next register toggle as the current field alternates.
In 3:2 pulldown, both the First Field bit and Last Field bit
are cleared when the current field is the middle field.
Field First
Host Top
4
Host Repeat
First Field
3
Description
Normal
Freeze Frame
Freeze Last Field
Freeze First Field and Hold
3:2 Pull Down
Bitstream
From
2
Freeze Mode [1:0]
1
R/W [1:0]
R/W 2
R/W 3
R/W 4
0
R 5