L64105 LSI Logic Corporation, L64105 Datasheet - Page 274

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 8.18
1. SDRAM addresses at 64-byte boundaries.
8.4.2 Reduced Memory Mode
8-32
Frame Store
A1
A2
A3
Frame Store Base Address Registers
Anchor Luma Frame Store 1 Base Address [7:0]
Anchor Luma Frame Store 1 Luma Base Address [15:8]
Anchor Chroma Frame Store 1 Base Address [7:0]
Anchor Chroma Frame Store 1 Base Address [15:8]
Anchor Luma Frame Store 2 Base Address [7:0]
Anchor Luma Frame Store 2 Base Address [15:8]
Anchor Chroma Frame Store 2 Base Address [7:0]
Anchor Chroma Frame Store 2 Base Address [15:8]
B Luma Frame Store Base Address [7:0]
B Luma Frame Store Base Address [15:8]
B Chroma Frame Store Base Address [7:0]
B Chroma Frame Store Base Address [15:8]
The start addresses of frame stores A1, A2, and A3 are programmed by
the host using the registers listed in
In RMM, the anchor frames are reconstructed as described in the normal
mode, but the B frame reconstruction uses less than a full frame store.
This mode is used for decoding high-resolution pictures, such as for PAL
(720 x 576), using only 1M x 16 bits of SDRAM.
The host enables RMM by setting the Reduced Memory Mode bit in
Register 248
only when it encounters an anchor frame (I or P picture). The host
determines the amount of memory allocated to the B frame store by
writing a value into the Number of Segments in RMM field in Register
289
of the frame. The minimum and maximum number of segments can be
calculated using the following formulas:
Video Decoder Module
(page
4-68). Each segment consists of a frame store for eight lines
(page
Address
4-58). This register is read by the Video Decoder
1
Table
8.18.
1
Register
224
225
226
227
228
229
230
231
232
233
234
235
Page Ref.
4-48
4-48
4-48
4-49
4-49
4-49