L64105 LSI Logic Corporation, L64105 Datasheet - Page 431

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

idle states
IEC
IEC - host copyright bit
IEC - host emphasis bits
IEC - overwrite copyright bit
IEC - overwrite emphasis bit
IEC958
IEC958 bitstream conversions 10-19,
IEC958 channel status
IEC958 formatted output
IEC958 stream syntax
IEC958 syntax
ignore sequence end bit
illegal bit error interrupt bit
image data
image formats
images
subframe preamble
bitmap overlays 9-23,
borders
color selection
continuous skipping 4-50,
current frame
current image
display areas
display override 4-59, 8-41,
display rates 8-24,
fast forward
force broken link
frame center offsets
frame override
horizontal scaling
horizontal/vertical offset
ignore sequence end
large
location
motion compensation
quality
reconstructing 2-7, 2-12, 6-29, 8-24,
repeating 4-51,
B-4
external OSD controller
B pictures 8-43,
chroma frame stores
error detection
force rate control
interlaced modes
luma frame stores
output bus
portions
refreshes and
rip forward mode and
start command
tearing problems
B-4
9-19
9-16
4-39
9-13
9-2
8-18
9-24
9-34
10-31
4-52
9-5
4-53
4-53
2-8
2-8
4-68
4-52
4-54
4-41
9-20
4-78
4-57
9-30
10-30
9-19
10-31
10-32
4-87
8-16
4-54
8-43
8-31
Index
4-55
4-55
2-11
4-54
4-87
7-9
9-24
4-8
9-6
7-9
4-88
8-41
4-87
4-51
9-32
9-15
10-21
9-30
impulse response A
impulse response B
initial pixel state
initializing display parameters
initiate memory test bit
input
input bitstream
input FIFO See FIFO buffers
input formats
input signals
inputs
integrated circuits
Intel-type processors 1-2,
resolution 1-5, 1-7, 9-16,
resolution enhancing
scaling 9-6,
sequence end code 4-3,
single step command bit
single step status
size 1-5, 7-9,
skipping 4-50,
small
source/target ratios
start code sequences
still 8-46, 9-6,
wide
audio bits
DAC interface
DREQn signal as
external OSD mode
horizontal timing
S/P DIF interface
sync timing
vertical sync pulse
parsing
types described
audio interface
channel interface
host interface
video interface
AC testing
AC timing
data acknowledge/ready
enabling
host signals listed
pin/write indicator
read cycles timing diagram
bitstream sample
enhancing
raster mapper increments
reducing
raster increment values and
doubling
9-32
9-13
10-12
2-3
11-18
7-7
4-12
11-12
11-4
9-10
4-12
9-15
9-16
9-20
9-11
9-15
2-3
9-23
9-13
8-35
10-27
9-31
2-8
2-9
6-1
9-11
9-21
9-22
2-5
10-29
5-14
4-53
2-4
5-2
4-68
to
9-20
4-92
9-32
10-3
9-18
8-27
9-15
5-2
2-4
8-46
4-53
9-17
9-4
11-13
9-22
9-23
IX-15