L64105 LSI Logic Corporation, L64105 Datasheet - Page 182

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.3.2 SCR Registers
5-6
When any of the interrupt bits in the first few registers are set, the
L64105 also asserts the INTRn output signal to the host. The INTRn
signal alerts the host to read the interrupt registers to determine the
reason for the interrupt and take the necessary action. Any of these
interrupts can be masked to prevent the assertion of INTRn for that
condition.
The control bits and fields allow the host to determine the modes of
operation of the chip. Many of these also serve to show the current status
of the chip.
As the input bitstream is parsed, address pointers to the different header
fields and data elements in the SDRAM buffers are written to registers
by the chip as information to the host. The host can write to some of
these registers to specify the start and end addresses of the various
header and data buffers in SDRAM.
The L64105 contains a 32-bit, free-running counter for maintaining a
System Clock Reference. This counter is incremented every 300 clock
cycles and serves as the basic time reference for the device. The SCR
counter has a number of features which enhance the synchronization of
audio and video.
counter circuits.
The general operating mode depends on the host’s setting of the SCR
Compare/Capture Mode bits in Register 17. The bit assignments and
modes are listed in
Table 5.2
Host Interface
Mode Bits Mode
0b00
0b01
0b10
0b11
No compare and capture happens. SCR overflow works.
Capture mode
Compare mode
Reserved
SCR Compare/Capture Mode Bits
Figure 5.6
Table
5.2.
shows the functional operation of the SCR