L64105 LSI Logic Corporation, L64105 Datasheet - Page 185

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.3.3 Interrupt Registers
Figure 5.7
Mask Register
Event
Host Write
Interrupt/
“Sticky”
Status
Bit
Interrupt Structure
Interrupt
Mask
Bit
In addition to the SCR Compare/Capture events, the L64105 uses other
events (single cycle internal pulses occurring at a specific time) to tell the
host when critical items have happened in the decoder. These events are
needed in various systems to signal error conditions, channel buffer
conditions, A/V sync information, and general data flow through the
decoder. The events can be used as interrupts or simply as status
information.
Registers 0 through 4 (see
These bits are set by the L64105 when their corresponding event occurs
and the INTRn interrupt output signal is asserted to the host if the event
is not masked.
Figure 5.7
interrupt/status bit in one of the host-accessible registers. If the interrupt
mask for that bit is not set by the host, the event is ORed with other
events to set one of the inaccessible IntReg registers. The outputs of
these registers are ORed and the result is inverted to assert the INTRn
output signal low.
When the host detects INTRn asserted, it reads all of the interrupt/status
registers to determine the cause of the interrupt and take any necessary
action. The host read clears the interrupt/status bit but does not clear the
associated IntReg. To deassert INTRn, the host must set the Clear
Interrupt Pin bit in Register 6.
Register Access and Functions
Host Read
Status Register
Events
Other
shows the interrupt structure. The event sets an
Chapter
Interrupt Pin
Host Clear
“Sticky”
Reg 1
Reg 2
Int
Int
4) contain 34 status/interrupt bits.
Registers
Interrupt
Other
INTRn
Pin
5-9