L64105 LSI Logic Corporation, L64105 Datasheet - Page 168

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 4.4
4-86
ACLK Divider
Select [3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7–0xB
0xC
ACLK Divider Select [3:0] Code Definitions
ACLK
Input
768 * Fs
768 * Fs
512 * Fs
384 * Fs
256 * Fs
768 * 48
512 * 48
Not Used
768 * 48
Register Descriptions
S/P DIF Interface BCLK DAC Interface BCLK DAC A_ACLK
128 * Fs = ACLK
128 * Fs = ACLK
128 * Fs = ACLK
128 * Fs = ACLK
128 * Fs = ACLK
128 * 48 = ACLK
128 * 48 = ACLK
128 * 32 = ACLK
Case IIA: The Linear PCM bitstream with a sampling
frequency of 96 kHz is selected and the external DAC
supports 96-kHz sampling frequency. ACLK_48 at a
multiple of 512 or 768 must be available and it must
be selected. Use divider code 0x5 for
ACLK = 768 * 48 or code 0x6 for ACLK = 512 * 48.
Case IIB: The Linear PCM bitstream with a sampling
frequency of 96 kHz is selected but the external DAC
does not support 96-kHz sampling frequency.
ACLK_48 must be available and it must be selected.
Set the Audio Decoder Mode Select field (Register
357, bits [7:5],
output samples to 48 kHz. Use the 0x0 through 0x4
divider code that matches the ACLK_48 multiple.
Case III: The input sampling rate is 32 kHz but
ACLK_32 is not available. Select ACLK_48 and the
0xC through 0xF divider code that matches the
ACLK_48 multiple to derive the 32-kHz clocks from
ACLK_48.
6
6
4
3
2
6
4
9
64 * Fs = ACLK
64 * Fs = ACLK
64 * Fs = ACLK
64 * Fs = ACLK
64 * Fs = ACLK
64 * 96 = ACLK
64 * 96 = ACLK
64 * 32 = ACLK
page
4-81) to 0b101 to decimate the
12
12
8
6
4
6
4
18
256 * Fs = ACLK
384 * Fs = ACLK
256 * Fs = ACLK
384 * Fs = ACLK
256 * Fs = ACLK
384 * 96 = ACLK
256 * 96 = ACLK
384 * 32 = ACLK
3
2
2
1
1
1
1
3