L64105 LSI Logic Corporation, L64105 Datasheet - Page 329

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 9.18 Freeze Operation Timing
Normal Sequence
Freeze 1st Field
Freeze Frame
Freeze Mode
Freeze Last
Odd/Even
& Hold
Field
O
T0
Normal
T0
T0
T0
The Freeze Mode bits are sampled at the field boundaries. However, only
freeze requests issued before the first field in the frame are applied to
the frame. That is, a freeze request issued during the first field is applied
to the next frame. The return to normal request, however, is honored at
the next field.
The host can detect the inversion condition by reading the First Field and
Top/Not Bottom Field bits in Register 275
opposite states, the fields are inverted. A single Freeze Last Field
request can correct the inversion. If the host sets the Automatic Field
Inversion Correction bit in Register 279
detected by the Display Controller, it displays the next frame starting at
display line two in the frame store.
The First Field bit in Register 275
Register 276 can be monitored by the host to determine which field in
the frame is currently being displayed. When both bits are cleared, a
middle field is being displayed as in pulldown or freeze modes.
Display Freeze
Note:
B0
B0
B0
B0
E
Freezing for an odd number of field times causes a field
inversion. A field inversion is defined as displaying the top
field of a frame during an even field time and the bottom
field during an odd field time.
O
T1
T1
T1
T1
Freeze Active
B1f
B1
T1f
B1
E
T1f
T2
T1f
B1f
O
(page
B1f
T1f
B1f
B2
(page
E
4-62) and Last Field bit in
(page
4-65) and field inversion is
T1
B1
T1
T3
O
Normal
4-62). If they are at
T2
B3
T2
T2
E
9-37