L64105 LSI Logic Corporation, L64105 Datasheet - Page 85

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.2
Read
Write
Compare
Compare
Interrupt
Mask
SCR
SCR
7
Register 1 (0x001)
Overflow
Overflow
Interrupt
First Slice Start Code Detect Interrupt
Sequence End Code Detect Interrupt
SDRAM Transfer Done Interrupt
Reserved
Audio Sync Recovery Interrupt
New Field Interrupt
Audio Sync Code Detect Interrupt
Host Interface Registers
Mask
SCR
SCR
6
Blank Mask
Interrupt
Vertical
Vertical
Begin
Blank
Begin
5
This bit is set when the decoder detects the first slice
start code after the picture layer. INTRn is asserted
unless the host sets the mask bit.
This bit is set when the decoder detects a sequence end
code. INTRn is asserted unless the host sets the mask
bit.
This bit is set when an SDRAM block move is completed.
INTRn is asserted unless the host sets the mask bit.
Set this bit when writing to Register 0.
The audio sync recovery bit is set when sync is re-
established after any errors, i.e., when three good frames
are detected after synchronization was lost.
This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.
This bit is set after a short delay after the termination of
the Vertical Sync pulse from the PAL/NTSC Encoder.
INTRn is also asserted unless the host sets the mask bit.
This bit is set when the Audio Decoder detects a valid
audio sync code. The interrupt is intended to be used for
synchronization of presentation units. This is achieved by
sampling the System Clock Reference (SCR) using the
capture register function of the SCR. Also at this time, the
Begin Active
Begin Active
Video Mask
Interrupt
Video
4
Reserved
Reserved
3
Audio Mask
Compare
Compare
Interrupt
Audio
SCR
SCR
2
Picture Start
Code Detect
Picture Start
Code Detect
Interrupt
Mask
1
Code Detect
Code Detect
Audio Sync
Audio Sync
Interrupt
Mask
0
4-3
2
3
4
5
6
7
0