L64105 LSI Logic Corporation, L64105 Datasheet - Page 99

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.16
4.2 Video Decoder Registers
Figure 4.17
7
7
Reserved
Register 29 (0x01D) Audio Channel Bypass Data [7:0]
Register 64 (0x040)
Setting the Channel Bypass Enable bit (bit 3 in Register 5 -
allows the host to write data directly to the video channel through this
register, bypassing the parallel channel input port.
Setting the Channel Bypass Enable bit (bit 3 in Register 5 -
allows the host to write data directly to the audio channel through this
register, bypassing the parallel channel input port.
Registers 30–63
Aux Data FIFO Status [1:0]
Reset Aux Data FIFO
Video Decoder Registers
5
Audio Channel Bypass Data [7:0]
The states of these bit indicate the status of the Aux Data
FIFO as shown in the following table. Once “overrun”
(0b11) occurs, the status stays at overrun until the
register is read.
Bits
0b00
0b01
0b10
0b11
Writing a 1 to this bit resets the Aux Data FIFO to empty.
Any data in the FIFO at this time is lost.
4
Reserved
Aux Data Layer ID [2:0]
W
Status
Empty
Data ready
Full
Overrun
2
Aux Data FIFO Status [1:0]
Read Only
1
R
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page
Data FIFO
Reset Aux
R [1:0]
W
4-10)
4-10)
0
0
[7:0]
W 0
4-17