L64105 LSI Logic Corporation, L64105 Datasheet - Page 33

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2.2 Host Interface
BUSMODE
CSn
A[8:0]
ASn
D[7:0]
DSn/WRITEn Data Strobe/Write Indicator
Host Interface
Host Controller Select Pin
This pin must be tied to VSS if the host CPU is an Intel
processor or to VDD if it is a Motorola processor. The
Intel processor uses two separate pins, READn and
WRITEn, for read and write transfers. The Motorola
processor uses a single read/write signal, READ.
Chip Select
This active-LOW signal indicates an attempt by an
external host CPU to access the L64105 either for a read
or a write bus cycle. CSn must be asserted for the entire
read/write cycle and may held LOW for more than one
bus transaction.
Address
Nine-bit address input selects one of 512 internal
registers. The address value on these lines is latched on
the falling edge of READn in a read cycle and on the
falling edge of WRITEn in a write cycle in Intel mode.
Motorola mode uses a separate address strobe, ASn.
Address Strobe
Active-LOW address strobe input. This signal is used in
Motorola mode to latch the address.
Host Data Bus
The host uses the D[7:0] bidirectional data bus to
program the L64105 and access status and bitstream
information during operation. During a read bus cycle,
D[7:0] carries valid information from an internal L64105
register. DTACKn/RDYn or WAITn indicate when the data
on the bus is valid. In write cycles, the data is latched by
the L64105 on the rising edge of DSn/WRITEn.
DSn - Motorola Mode
DSn indicates when the host strobes the data in or out of
the L64105. Read transactions start when DSn, CSn, and
ASn are all LOW. During a write cycle, the L64105
latches the data on the bus on the rising edge of DSn.
Bidirectional
Input
Input
Input
Input
Input
2-3