L64105 LSI Logic Corporation, L64105 Datasheet - Page 425

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

current frame
current picture
D
D[7:0] signal
DAC
DAC clock 2-10, 10-6,
DAC interface
DAC mode selection
DAC output mode timing
data block copies
data bus 2-3, 2-6, 2-7,
data pattern for RAM bits
data rates
data strobe
data transfers 1-3, 5-12,
description
CD player
samples
features
overview
PCM samples
soft-muting scheme
16 bit
20 bit
24 bit
See also bus
current byte
luma/chroma output
L64105
MPEG-1
MPEG-2
asynchronous
current state
host interface
maximum transfer rate
request signal
S/P DIF interface
status 4-10,
synchronization
synchronous 2-6, 4-28, 4-29, 4-89,
B-2
block copies
transfer count 5-15,
external DMA
video requests
channel buffering
A/V data valid
A/V event interrupts 4-6,
A/V read compare
AC timing
audio code detect
audio sync errors 4-8,
10-27
10-28
10-28
A-1
10-2
2-3
2-10
A-1
A-1
10-5
2-3
4-53
2-9
2-3
10-27
4-53
4-38
9-39
4-39
11-14
5-14
6-4
10-16
2-5
5-18
5-18
2-5
to
4-81
10-8
2-6
2-6
to
10-33
7-1
10-29
10-29
9-10
7-7
Index
6-1
4-4
5-18
4-21
4-92
6-3
5-16
10-5
4-7
6-5
DC coefficient
DCK input
DCK signal
DCSQ
DCT
DCT coefficients
decimation filter 4-61,
decode start delay
decode start/stop command write bit
decode status interrupt bit
decode stop command
Decode Time Stamp See DTS
decode/display frame bits
decoder chip overview
decoder output
decoder play mode status bit
decoders See specific decoder
decode-to-display pacing
decompression
default category 4-88,
default values
delays 4-43,
demultiplexer
device clock 2-12, 9-6,
devices
diagnostic mode
synchronous recovery bit
data transfers synchronous and
asynchronous mode
asynchronous transfers
description
maximum frequency
synchronous mode
synchronous transfers 6-5,
programmable backgrounds
video display 9-4,
external OSD
DAC interface output
S/P DIF interface input
recommended connection
See also external devices
SDRAM
clock synchronization
internal phase states
programmable delays
SDRAM internal state
B-2
channel constraints
hardware sync controls and
input timing 9-10,
out-of-sync conditions
PCM data
timing
constraints
B-2
6-3
2-6
7-3
8-34
11-15
6-24
A-4
8-14
2-6
1-4
1-2
A-4
10-16
9-32
6-7
7-8
9-5
9-20
10-32
6-3
1-2
9-10
9-15
6-3
6-7
9-11
4-45
10-27
4-44
8-24
4-44
4-44
8-34
6-6
4-2
10-29
to
6-5
10-5
4-3
1-5
4-78
2-8
6-7
4-60
2-10
2-6
4-57
IX-9