L64105 LSI Logic Corporation, L64105 Datasheet - Page 358

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.7 PCM FIFO Mode
10-26
The host can write four-byte, L-R PCM samples (two bytes for each
channel) into the PCM FIFO and select these values to play through the
Linear PCM Decoder. The registers associated with PCM FIFO mode are
listed in
status bits and monitor the near full signal (PREQn) for external DMA
control.
Table 10.9
The host uses the following sequence for PCM FIFO mode:
1. Clear the Decode Start/Stop Command bit to stop the Audio
2. Program the Audio Decoder Mode Selection bits to 0b111 to select
3. Using a host DMA controller, write PCM audio into the PCM FIFO
4. Set the Decode Start/Stop Command bit to start the Audio Decoder.
5. Monitor the PCM FIFO status bits in Register 353 and the PREQn
Audio Decoder Module
Register
264
357
359
353
Decoder.
the PCM FIFO mode.
Data In register to fill the PCM FIFO. The audio data is written in the
following order; left channel LSB, left channel MSB, right channel
LSB, and right channel MSB. The PCM FIFO is 16 words deep x
16 bits wide.
output signal of the L64105. The PCM FIFO Near Full bit is cleared
when the PCM FIFO contains less than 25 unread words. When the
bit is cleared, PREQn is also asserted to the external DMA controller.
Table
PCM FIFO Mode Registers
[7:5]
[7:0]
Bits
10.9. The host can read the FIFO full, near full, and empty
0
7
6
5
Name
Decode Start/Stop Command
Audio Decoder Mode Select [2:0]
PCM FIFO Data In [7:0]
PCM FIFO Full
PCM FIFO Near Full
PCM FIFO Empty
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