L64105 LSI Logic Corporation, L64105 Datasheet - Page 37

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2.4 Memory Interface
Important:
SCSn
SCS1n
SDQM
SBA[11:0]
SCASn
SRASn
SBD[15:0]
Memory Interface
The length of all connections between the L64105 and
SDRAM on a PCB layout must be kept as short as
possible, must be matched in length and pin load, and the
pin load should be less than 50 pF.
SDRAM Chip Select
The host asserts this signal to select the low address
SDRAM chip, the first 2 Mbytes of memory. The
recommended SDRAM size for the L64105 is:
Second SDRAM Chip Select
The host asserts this signal to select the high address
SDRAM chip in systems that have more than
2 Mbytes of memory. The high address SDRAM chip
must have the same page size as the low address
SDRAM chip but does not have to have the same number
of pages.
SDRAM Control Pin
SDQM is an active HIGH output signal for the SDRAM
data control mask.
SDRAM Address Bus
The row/column multiplexed address bus for SDRAM
memory. The L64105’s microcontroller and the host
address SDRAM as if it were RAM. The Memory
Interface converts these addresses to SDRAM format.
SDRAM Column Address Select
The Memory Interface asserts this signal when the
SDRAM column address is on SBA[11:0].
SDRAM Row Address Select
The Memory Interface asserts this signal when the
SDRAM row address is on SBA[11:0].
SDRAM Data Bus
This 16-bit bidirectional data bus is directly connected to
1M x 16 SDRAM(s) for buffering channel data and
reconstructed pictures.
2048 512 16 bits
Bidirectional
Output
Output
Output
Output
Output
Output
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