L64105 LSI Logic Corporation, L64105 Datasheet - Page 360

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 10.11 DAC Output Mode: PCM Sample Precision = 20 Bit
(Invert LRCLK=0)
(Invert LRCLK=1)
Figure 10.12 DAC Output Mode: PCM Sample Precision = 24 Bit
(Invert LRCLK=0)
(Invert LRCLK=1)
10-28
ASDATA
ASDATA
LRCLK
LRCLK
LRCLK
LRCLK
BCLK
BCLK
Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
Right PCM
Right PCM
Right PCM
Right PCM
R1
R1
N-1
N-1
N-1
N-1
R0
R0
The interface supplies four signals to the DAC:
BCLK and A_ACLK are derived from an ACLK input in the Clock Divider
(see
expressed as:
Audio Decoder Module
(Twelve sign extension bits)
(Eight sign extension bits)
S
S
a sample clock, A_ACLK,
the bit clock, BLCK,
a left/right channel clock, LRCLK, and
the serial audio data, ASDATA.
Section 10.10, “Clock
S
S
BCLK
S L19
S L23
Left PCM
Left PCM
Left PCM
Left PCM
=
N-1
N-1
N
N
Sample Freq Sample Resolution 2 channels
L18
L22
L1
L1
Divider”). BCLK is at the output bit rate and
L0
L0
(Twelve sign extension bits)
(Eight sign extension bits)
S
S
S
S
S R19 R18
S R23 R22
Right PCM
Right PCM
Right PCM
Right PCM
N
N
N
N
R1
R1
R0
R0
Left PCM
Left PCM
S
S
Left PCM
Left PCM
N+1
N+1
N
N
S
S