L64105 LSI Logic Corporation, L64105 Datasheet - Page 137

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

GOP User Data Only
Concealment Copy Option
Force Rate Control
Ignore Sequence End
Microcontroller Registers
reconstruction to the point where the picture starts
tearing since reconstruction is not able to keep pace with
the display. Eliminating the backward vectors reduces the
demand made on the SDRAM bandwidth by reducing
accesses to the reference anchor store in the SDRAM.
This should alleviate any tearing problems. However, this
does not completely guarantee solving any bandwidth
problems that may exist with slow SDRAM devices.
When this bit is set, the Video Decoder recognizes only
user data supplied in the GOP layer of the MPEG-1/
MPEG-2 video stream. User data of other layers, if
present, is discarded by the decoder and is not written to
the user FIFO. This feature is designed to accept only
line 21 data (closed-caption data) in a Set Top Box. By
discarding other user data layers, the processing
overhead on the host controller in a Set Top Box is
reduced significantly. The default value of this register at
start-up is 0, which means user data of all layers is
available to the host in the user FIFO.
When set, this bit overrides any concealment vectors that
may have been present in the original MPEG video
bitstream. Normally, MPEG specifies that these vectors
be used to conceal any errors that may be detected by
the decoder. When this bit is set, copying from the
previously decoded valid picture is used instead of
applying the concealment vectors. This register is cleared
by default (i.e., after reset or power-up).
When this bit is set, the decoder controls the rate of the
decoding process based on the display rate. When this
bit is cleared, the decoder controls the rate of the
decoding process only if it is accessing the same frame
store as the display process.
When this bit is set, the last picture of a sequence is not
displayed at the sequence end code but at the beginning
of the next sequence. When this bit is cleared, the
decoder displays the last picture of the sequence at the
sequence end code.
R/W 3
R/W 4
R/W 5
R/W 6
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