BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 205
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 205 of 959
- Download datasheet (5Mb)
TENTATIVE
TMPA900CM
3.10.2
Overview of MPMC0
MPMC0 contains both a DMC (Dynamic Memory Controller) that controls SDRAM and
SMC (Static Memory Controller) that controls NOR Flash and SRAM.
Features of a DMC (Dynamic Memroy Controller):
a. Supports 32-bit/16-bit SDR SDRAM
b. Supports 1 channel Chip Select
c.
Supports clock-basis adjusting function for SDRAM request timing.
Features of an SMC (Static Memory Controller):
(a) Supports asynchronous, 32-bit/16-bit SRAM and NOR Flash (only separate buses are
supported, and multiplex buses are not supported)
(b) Supports 2 channels Chip Select
(c) Cycle timings and memory data bus widths can be programmed for each Chip Select
TMPA900CM- 204
2009-10-14
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