BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 239
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.10.3.2 SMC (Static Memroy Controller)
Support memory
Data bus width
Access areas
Timing adjustment
Clock
External control pin
(NOR Flash memory, Mask ROM SRAM and etc.).
(1) SMC function outline
Table 3.10.6 shows features of SMC.
This device contains SMC (Static Memory Controller) that controls the external memory
External static memory (NOR Flash memory and SRAM, etc.)
Support separate bus only
16bit/32bit data bus width
2 areas supported by Chip select.
Max aceess area:
SMCCS0n: 512 MB
SMCCS1n: 512 MB
Adjustable AC timing by register
Support external wait request (only in Synchronous mode)
Selectable clock for external pin (f
CLKCR5<SEL_SMC_MCLK>
D31 to D0, A23 to A0,
SMCBE0n, SMCBE1n, SMCBE2n, SMCBE3n,
SMCCS0n, SMCCS1n,SMCOEn,SMCWEn
Table 3.10.6 Features of SMC
TENTATIVE
TMPA900CM- 238
HCLK
or f
Features
HCLK
/2) by the clock controller register
TMPA900CM
2009-10-14
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