BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 393

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e. <EPS>
f.
g. <BRK>
Note: When you set UARTxLCR_H, UARTxIBRD and UARTxFBRD, UARTxLCR_H must be set at the end.
register.
When this bit is set to 1, even parity generation and checking are performed during
transmission and reception. This function checks whether the number of 1s contained in
the data bits and parity bit is even. When this bit is cleared to 0, odd parity check is
performed to check whether the number of 1s is odd. This bit has no effect when parity is
disabled by Parity Enable bit <PEN> being cleared to 0. Refer to Table 3.13.2 for the truth
table.
<PEN>
When this bit is set to 1, parity check and generation are enabled. Otherwise, parity is
disabled and no parity bit is added to data frames. Refer to Table 3.13.2 for the truth table
of SPS, EPS, and PEN bits.
When this bit is set to 1, the UxTXD output remains LOW after the current character is
transmitted. For generation of the transmit break condition, this bit must be asserted
while at least one frame is or longer being transmitted. Even when the break condition is
generated, the contents of the transmit FIFO are not affected.
Table 3.13.2 is the truth table of the <SPS>, <EPS> and <PEN> bits of the UARTxLCR_H
enable(PEN)
When you update only UARTxIBRD or UARTxFBRD, UARTxLCR_H register must be set again.
Table 3.13.2 Truth table of UARTxLCR_H <SPS>, <EPS> and <PEN>
Parity
0
1
1
1
1
select(EPS)
Even parity
1
0
0
1
x
TENTATIVE
TMPA900CM- 392
Stick parity
(SPS)
select
x
0
0
1
1
Parity bit (transmitted or checked)
Not transmitted or checked
Even parity
Odd parity
1
0
TMPA900CM
2009-10-14