BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 685
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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[0]
Bit
8.
−
WATERMARK
−
LcdVComp
Reserved
Reserved
Reserved
BGR
LcdDual
LcdMono8
LcdTFT
LcdBW
LcdBpp
LcdEn
LCDControl (LCDC Control Register)
Symbol
Bit
Type
−
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
0y0
Undefined
0y00
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y000
0y0
Reset
Value
TENTATIVE
TMPA900CM- 684
Read as undefined. Write as zero.
LCD DMA FIFO watermark level
0y0:Requests DMA when space of 4 words or more occurs in either
0y1:Requests DMA when space of 8 words or more occurs in either
Read as undefined. Write as zero.
Interrupt occurrence timing
0y00: At vertical sync start
0y01: At back porch start
0y10: At display data start
0y11: At front porch start
Write as 1.
Write as 0.
Write as 0.
BGR system selected RGB
0y0: RGB normal output
0y1: BGR red/blue swap
STN panel select
0y0: Single panel LCD
0y1: Dual panel LCD
Selects the monochrome STN LCD parallel bit.
0y0: 4-bit interface for monochrome LCD
0y1: 8-bit interface for monochrome LCD
Selects the panel used for LCD.
0y0: STN panel
0y1: TFT panel
Selects monochrome or color for STN LCD.
0y0: Color
0y1: Monochrome
Number of LCD bits per pixel:
0y000 = 1 bpp
0y001 = 2 bpp
0y010 = 4 bpp
0y011 = 8 bpp
0y100 = 16 bpp
0y101 = 24 bpp (TFT panel only)
0y110 = Reserved
0y111 = Reserved
LCD controller enable:
0y0: Disable
0y1: Enable
of the two FIFOs.
of the two FIFOs.
Description
Address = (0xF420_0000) + (0x001C)
TMPA900CM
2009-10-14
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