BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 47

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.3
Memory Map
The memory map of TMPA900CM is as follows:
CPU data bus width
CPU address width
Minimum bus cycle
Internal Boot ROM
Internal operation
Internal RAM
Internal I/O
frequency
Item
Table 3.3.1 Outline of access to internal area
TENTATIVE
TMPA900CM- 46
32-bit,1-HCLK
32-bit,2-PCLK
clock access
clock access
1-f
CLK
32-bit 1-HCLK clock access
32-bit 1-HCLK clock access
Max 150MHz @ -20 to 85°C
Max 200MHz @ 0 to 70°C
clock access (5ns at 200MHz)
Outline of access
32 bit
32 bit
A/D C, TSI, Timer/PWM, PMC,
LCDC, LCDDA, INTC, DMAC,
USB Device, USB Host, I
System C, PLL CG, GPIO
I
2
C, UART, RTC, WDT,
SSP,CMSIF,MPMC
NANDFC, SDHC,
TMPA900CM
2009-10-14
2
S,

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