BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 207

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMAC2 bus request
LCDDA bus request
USB bus request
DMAC1 bus request
(b)
Handling priority : ①→②→③→⑤→④
2. Bus matrix 2 of LCDDA, DMAC1, DMAC2 and USB handles the earliest bus
1. Dynamic memory clock: Use HCLK clock
2. Static memory clock: Use HCLK or 1/2 HCLK
Clock Variety
request first. If multiple bus requests are accepted simultaneously, they are
prioritized as shown below.
LCDDA > USB > DMAC1 > DMAC2
Following diagram show the priority of bus request.
Control clock is controlled in PLLCG circuit.
dotted line is the point of handling end、bus is released
①
③
④
②
TENTATIVE
LCDDA
handling
TMPA900CM- 206
(Set CLKCR5<SEL_SMC_MCLK>)
USB
handling
DMAC1
handling
⑤
LCDDA
handling
DMAC2
handling
TMPA900CM
2009-10-14