BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 338

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLLCG
f
32kHz
PCLK
3.12.2
CLKCR5
register
INTS [2]
/2
programmable 16-bit free-running decrement counters. The TIMCLK input is used for counter
operation. This clock can be selected from the internal system clock divided by two (f
fs (32.768 kHz).
Figure 3.12.1 shows a diagram of the timer block (Timer 0 and Timer 1).
APB
Each timer block, containing two channels of timer circuits, is comprised of two
The timer clock (TIMCLK) is generated by a prescale unit.
Block Diagrams
T0: f
T16: f
T256: f
PCLK
PCLK
TIMCLK
PCLK
generation
Read data
/2
Decoder
Address
Timer1 interrupt
Timer0 interrupt
/2 divided by 16, generated by a 4-bit prescaler.
Figure 3.12.1 Timer Block Diagram (Timer 0 and Timer 1)
/2 divided by 256, generated by an 8-bit prescaler.
TENTATIVE
TMPA900CM- 337
TIMCLK
TIMCLK
Divide
by 16
Divide
by 16
Divide
by 16
Divide
by 16
T256
T256
T16
T16
T0
T0
Timer 0
Control
Timer 1
Control
Interrupt
Generation
Interrupt
Generation
Timer 0
Timer 1
16-bit down counter
16-bit down counter
Timer 0
Load
Timer 1
Load
Timer 1
Value
Timer 0
Value
TMPA900CM
2009-10-14
PCLK
Timer 0
Compare
/2) and
PWM Out