BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 209
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 209 of 959
- Download datasheet (5Mb)
AHB
Domain
DMC
I/F
(2) DMC block diagram
Manager
(a) Arbiter
(b) Memory manager
Memory
and after access arbitration, it passes the highest priority command to the memory I/F.
The arbiter receives access commands from the DMC I/F and the memory manager,
Data is read from the memory I/F to the DMC I/F.
The memory manager monitors and controls status of DMC block.
Figure 3.10.2 is a DMC block diagram.
Arbiter
Figure 3.10.2 DMC Block Diagram
TENTATIVE
TMPA900CM- 208
APB Slave
APB I/F
I/F
Memory I/F
PAD I/F
APB
Domain
External
memory I/F
EBI I/F
Memory
Domain
TMPA900CM
2009-10-14
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