BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 680

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

b. <CPL>
c.
d. <IPC>
e. <IHS>
f.
This value is obtained by dividing the number of pixels per line by 1, 4, 8 or 8/3, and then
subtracting one from the quotient. To allow the LCD controller to function properly, this
field needs to be programmed properly in addition to PLL.
display data is available. It can be used only for TFT displays.
TFT
STN
<IOE>
This bit set the panel clock edge.
This bit set the polarity of Horizontal sync signal.
<IVS>
This bit set the polarity of Vertical sync signal.
The IOE bit specifies the polarity of the data enable signal.
The CPL field specifies the actual number of LCLCP clocks per line in the LCD panel.
The data enable signal is output on the LCLAC pin to notify the LCD panel when valid
Panel Type
Monochrome
Color
Bus Width
－
4
8
8
TENTATIVE
TMPA900CM- 679
Note: Round up all digits to the right
CPL =
CPL =
CPL =
CPL =
of the decimal point.
(Number of pixels per line)
(Number of pixels per line)
(Number of pixels per line)
(Number of pixels per line)
CPL Calculation Formula
1
4
8
8
3
－1
－1
－1
－1
TMPA900CM
2009-10-14