BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 490

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.16.2.2 Overall Composition
3.16.2.3 Clock Domain
CLK_U: 30 MHz (to be supplied by USB 2.0 PHY)
CLK_H: HCLK
UDC2AB internal registers and UDC2 registers and the AHB Master function that
controls the DMA access to the UDC2 Endpoint I/F.
UDC2) and Master Write Channel (UDC2 to AHB), which enable DMA transfer
between the Endpoint I/F of Rx-EP and Tx-EP of UDC2. Each channel has two built-in
8-word buffers (four in total).
UDC2AB mainly consists of the AHB Slave function that controls the access to the
The AHB Master function has two built-in channels; Master Read Channel (AHB to
TENTATIVE
TMPA900CM- 489
TMPA900CM
2009-10-14

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