BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 940

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
No.
4.3.4
Measuring condition
Loaded capacitance
10 CKE set-up time
11 Command set-up time
12 Command hold time
1 CLK cycle time Note)
2 DMCSCLK high level width
3 DMCSCLK low level width
4 Access time from CLK(CL* =2)
5 Data hold time from internal read
6 Data set-up time
7 Data hold time
8 Address set-up time
9 Address hold time
Connection
Software configuration
Note: The “Equation” column in the table shows the specifications under the conditions DVCCM = 3.0 V to 3.6 V and
*CL = CAS latency
Note: The internal bus cycle is T=10ns minimum value when the guaranteed temperature is 0 to 70 degree.
The internal bus cycle is T=13.3ns minimum value when the guaranteed temperature is -20 to 85 degree.
SDR SDRAM Controller Electrical Characteristics
DMCSCLK pin: CL = 15pF
Others: CL = 25 pF
AC measurement conditions
• The letter “T” used in the equations in the table represents the period of internal bus frequency (f
• Output level: High = 0.7 × DVCCM, Low = 0.3 × DVCCM
• Input level: High = 0.9 × DVCCM, Low = 0.1 × DVCCM
which is one-half of the CPU clock (f
DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V.
1. DVCC3IO × 0.7 ≤ SELDVCCM ≤ DVCC3IO
2. DVSSCOMx ≤ SELMEMC ≤ DVCC3IO × 0.3
3. DMCCLKIN pin connect to DVSSCOMx
1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive)
2. dmc_user_config_3 = 0x0000_0001 (32bit bus width memory)
Parameter
dmc_user_config_3 = 0x0000_0000 (16bit bus width memory)
Symbol
TMPA900CM- 939
TENTATIVE
t
t
t
CMH
t
t
t
t
t
t
t
CKS
CMS
t
t
CK
CH
AC
HR
DS
DH
AH
CL
AS
FCLK
0.5T − 1.5
0.5T − 1.5
0.5T − 3.0
0.5T − 4.0
0.5T − 3.0
0.5T − 4.0
0.5T − 3.0
0.5T − 3.0
0.5T − 4.0
).
Min
2.0
T
Equation
T − 4.0
Max
100 MHz 96 MHz
3.5
3.5
6.0
2.0
2.0
1.0
2.0
1.0
2.0
2.0
1.0
10
10.4
3.7
3.7
6.4
2.0
2.2
1.2
2.2
1.2
2.2
2.2
1.2
TMPA900CM
2009-10-14
Unit
HCLK
ns
),

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