BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 70

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<PLLON>
PLL output: f
Lock-up timer
<LUPFLAG>
CPU clock f
<FCSEL>
PLL output: f
CPU clock f
<FCSEL>
<PLLON>
Note: When switching <FCSEL> from 1 to 0, a few clock cycles are required before f
FCLK
Setting example – 2: PLL stop
LUP:
PLL
the register write is completed. Therefore, it is necessary to first wait for the required clock cycles and then
execute the next instruction. More specifically, execute 10 NOP instructions.
FCLK
PLL
(SYSCR2)
Dummy instruction execution (Note)
(SYSCR3)
Switch from 192 MHz to 24 MHz
start
PLL operation and lock-up
替
Count up at f
←
←
TENTATIVE
TMPA900CM- 69
0x0000_0000
0x0000_0007
OSCH
During lock-up
PLL operation stop
; <FCSEL> = 0 (change from 192 MHz to 24 MHz)
; <PLLON> = 0
Lock-up end
Switch from 24 MHz to 192 MHz
After lock-up
替
FCLK
is changed to f
TMPA900CM
2009-10-14
OSCH
after