BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 772

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[Explanation]
a. <CSFOW>
b. <CSINTF>
c. <CFINTF>
d. <CSINTM>
e. <CFINTM>
f. <CDEDLY>
g. <CVSYPH>
Switches the windows of the FIFO buffer read registers.
0y0: 4 bytes (However, the high-order 1 byte is invalid data when RGB888)
0y1: Byte (The high-order 3 bytes are invalid data)
Shows the state of CMOS input signal sync interrupts during read; and clears interrupt
flags during write.
During READ
0y0: No sync interrupt
0y1: With sync interrupt
Shows the state of FIFO interrupts during read; and clears interrupt flags during write.
During READ
0y0: No FIFO interrupt
0y1: With FIFO interrupt
Sets the mask for CMOS input signal sync interrupts.
0y0: Sync interrupt masked
0y1: Sync interrupt enabled
Sets the mask for FIFO interrupts.
0y0: FIFO interrupt masked
0y1: FIFO interrupt enabled
Captures a valid signal capture point after a delay of one clock.
0y0: Normal
0y1: 1-clock delay
Selects the positive/negative logic of the vertical sync signal CMSVSY.
0y0: Negative logic (Negative)
0y1: Positive logic (Positive)
TENTATIVE
TMPA900CM- 771
During WRITE
0y0: Interrupt flag clear
0y1: Invalid
During WRITE
0y0: Interrupt flag clear
0y1: Invalid
TMPA900CM
2009-10-14