BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 513

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31]
[30:29]
[28]
[27:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
Bit
[Description]
abt_en
−
abtmod
−
abtpri_w1
−
abtpri_w0
−
abtpri_r1
−
abtpri_r0
a. <abt_en>
Symbol
10. ARBTSET (Arbiter Setting register)
Enables the arbiter operation when making an access between DMAC and AHB.
0 should be set to this bit when setting the abtmod and abtpri_* bits of this register.
Please note that 1 cannot be set to this bit in case values set for abtpri_* overlap.
Be sure to set this bit to 1 before starting a DMA access.
0y0: Disable (DMA access not allowed)
0y1: Enable
make an access three times in total.):
(1) Write 0 into the abt_en bit to disable the arbitration circuit.
(2) Make settings for the abtmod and abtpri_* bits.
(3) Write 1 into the abt_en bit with the abtmod and abtpri_* bits set in (2) retained to
Bit
The register for setting the priority when the internal arbiter accesses AHB.
Setting of this register should be changed after stopping the Master operation.
Please be sure to set the arbitration method with the following procedures (You need to
The abtmod and abtpri_* bits cannot be set unless 0 is written into the abt_en bit in (1).
Values of the register for setting the priority should not be overlapped regardless of the
value of the abtmod bit.
enable the arbitration circuit.
R/W
−
R/W
−
R/W
−
R/W
−
R/W
−
R/W
Type
0y1
Undefined
0y0
Undefined
0y11
Undefined
0y10
Undefined
0y01
Undefined
0y00
TENTATIVE
TMPA900CM- 512
Reset
Value
Arbiter enable
0y0: Disable (DMA access not allowed)
0y1: Enable
Read as undefined. Write as zero.
Arbiter mode
0y0: Round-robin
0y1: Fixed priority
Read as undefined. Write as zero.
Master Write 1 priority
0y00 to 0y11
Read as undefined. Write as zero.
Master Write 0 priority
0y00 to 0y11
Read as undefined. Write as zero.
Master Read 1 priority
0y00 to 0y11
Read as undefined. Write as zero.
Master Read 0 priority
0y00 to 0y11
Address = (0xF440_0000) + (0x003C)
Description
TMPA900CM
2009-10-14