BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 268

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:22]
[21:20]
[19:18]
[17:16]
[15:14]
[13:0]
[Description]
Bit
a. <memory_cmd>
Note: Use dmc_direct_cmd_5 to configure cas latency of DDR_SDRAM memory,
3.
This register sets each command for external memory and external memory mode register.
This register sets the initial setting of external memory.
Determines the command required:
0y00 = Prechargeall
0y01 = Autorefresh
0y10 = Modereg or Extended modereg
0y11 = NOP
memory.
Examples:
dmc_cas_latency_5 ← 0x00000004 (set memory controller CL = 2)
dmc_direct_cmd_5 ← 0x00080033
The setting of cas latency(CL) is different from SDR_SDRAM.
The CL setting value of memory controler must be 1 smaller than the CL setting value of DDR_SDRAM
dmc_direct_cmd_5 (DMC Direct Command Register)
−
chip_nmbr
memory_cmd
bank_addr
−
addr_13_to_0
Symbol
Bit
−
WO
WO
WO
−
WO
Type
TENTATIVE
TMPA900CM- 267
Undefined
−
−
−
Undefined
−
(set DDR SDRAM memory CL = 3)
Reset
Value
Read undefined. Write as zero.
Always write 0y00
Determines the command required:
0y00 = Prechargeall
0y01 = Autorefresh
0y10 = Modereg or Extended modereg
0y11 = NOP
Bits mapped to external memory bank address bits when
command is Modereg access.
0y00 = bank0
0y01 = bank1
0y10 = bank2
0y11 = bank3
Read undefined. Write as zero.
Bits mapped to external memory address bits [13:0] when
command is Modereg access.
Description
Address = (0xF431_0000) + (0x0008)
TMPA900CM
2009-10-14