BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 874

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AHB
Bus
3.27 USB Host Controller
3.27.1
3.27.2
Open HCI Specification Release 1.0a and supports USB transfers at 12 Mbps (full-speed).The
USBHC is connected to the Multi layer Bus System via on-chip SRAM.
The USB Host Controller (USBHC) is compliant with the USB Specification Revision 2.0 and the
The USBHC is subject to some restrictions. For details, see section 3.27.8.
(1) Supports full-speed (12 Mbps) USB devices. But Not supports Low-Speed (1.5Mbps)
(2) Supports control, bulk, interrupt and isochronous transfers.
(3) Contains two 16-byte FIFO buffers (IN and OUT) in the bus bridge logic for connecting with
(1) USBHC core (OHCI)
(2) USB transceiver
(3) CPU bus bridge logic
INTS [27] (INTUSB)
(4) Supports data transfers between the FIFO buffers in the bus bridge logic and the on-chip
SRAM.
On Chip RAM
(Internal RAM-1: 8 Kbyte)
0xF800_8000-0xF800_9FFF
The key features of the USBHC are as follows:
The USBHC consists of the following three blocks:
AHB Bus
the CPU, allowing a maximum of 16-byte burst transfers.
System Overview
System Configuration
Figure 3.27.1 USB Host Controller
Bus
Bridge
AHB
Slave
I/F
TENTATIVE
TMPA900CM- 873
USBHC Core
Buffer
USB Vbus ON Signal
Overcurrent Signal
USB Transceiver
Transceiver
USB
TMPA900CM
2009-10-14
HDM
USBOCn
HDP
USBPON