BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 686
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 686 of 959
- Download datasheet (5Mb)
Panel data
LCD [23:0]
Panel clock
LCLLP
LcdVcomp interrupt timing
(This timing delay about 3 HCLK from LCLLP edge)
Signal name
Vertical sync
signal
LCLFP
Back porch start
Front porch start
Vertical sync start
Display data start
[Description]
a. <WATERMARK>
b. <LcdVComp>
LCD DMA FIFO watermark level
0y0: Requests DMA when space of 4 words or more occurs in either of the two FIFOs.
0y1: Requests DMA when space of 8 words or more occurs in either of the two FIFOs.
0y00: At vertical sync start
0y01: At back porch start
0y10: At display data start
0y11: At front porch start
Following timing chart shows interrupt generation timing .
(Vertical sync
VSW + 1
pulse)
Vertical non-data area
(Vertical back porch)
VBP
TENTATIVE
TMPA900CM- 685
(Number of lines per panel)
LPP + 1
(Vertical front porch)
Vertical non-data area
VFP
TMPA900CM
2009-10-14
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