BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 309

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

b. Reading data from the NAND-Flash memory in page units and writing data to the built-in
Note: Please use the DMA function for the data read that uses the Autoload function.
RAM
implemented by using the built-in DMA controller in addition to two 32bit × 4word FIFOs
contained in the NDFC and the Autoload function.
rising edge of the NDRB pin in the state of NDFMCR1<ALS>= 1, the settings of steps (1)
and (2) below must be performed after command setting to the NAND-Flash before address
setting.
(1) Assign the NDFC to an arbitrary channel of the DMA controller and set the relevant
(2) Write 0 to the NDFMCR1<SELAL> register and 1 to the NDFMCR1<ALS> register.
In this section, a high-speed data read function with a smaller burden to the CPU is
Because the Autoload function at data read starts automatically after detection of a
and after detecting a rising edge, starts a read cycle of 1-byte data. Each time the
NDFC reads 1-byte data, it stores the read data in the first-stage 16-byte FIFO
(FIFO-0) and generates the ECC by entering the data to either Hamming Code ECC
calculator or Reed-Solomon ECC calculator depending on the setting of the
NDFMCR1<ECCS> register.
continued data read. In addition, the NDFC asserts a DMA transfer request to the
DMAC at the fill-up of FIFO-0 to request the transfer of the FIFO-0 data to the built-in
RAM.
FIFOs in this way.
termination interrupt and the CPU uses the interrupt to start the next process.
registers.
The following is an example in which the NDFC is assigned to DMAC channel 0:
DMACC0SrcAddr
DMACC0DestAddr
DMACC0Control
DMACC0Configuration ← <FlowCntrl[13:11]> = 0y010 (Peripheral to Memory),
When Step (2) is performed, the NDFC begins detecting a rising edge of the R/B pin,
When FIFO-0 is filled up with data, the FIFO-1) takes over the data storage for
Data can be read efficiently at a higher speed by switching between two 16-byte
When a total of 512 bytes of data has been read, the DMAC asserts a DMA
TENTATIVE
← <Swidth[2:0]> = 0y010 (32 bits),
← Address of NDFDTR
← Address of the built-in RAM
TMPA900CM- 308
<SBSize[2:0]> = 0y001 (4 beats),
<TransferSize[11:0]> = 0x80 (512 Bytes/ 4 Bytes)
<Dwidth[2:0]> = 0y010 (32 bits),
<ITC> = 1 (DMA termination interrupt is enabled.)
TMPA900CM
2009-10-14