BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 883

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31]
[30]
[29:7]
[6]
[5]
[4]
Bit
4.
event occurs, the Host Controller sets the corresponding bit in this register. When a bit is
set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable
register and the MasterInterruptEnable bit is set. The Host Controller Driver may clear
specific bits in this register by writing 1 to bit positions to be cleared. The Host Controller
Driver may not set any of these bits. The Host Controller will never clear the bit.
This register provides status on various events that cause hardware interrupts. When an
HcInterruptStatus Register
Mnemonic
－
OC
RHSC
FNO
UE
Rese
rved
31
15
R/W
R/W
OC
30
14
0
Reserved
Ownership
Change
Reserved
RootHubStatus
Change
FrameNumber
Overflow
Unrecoverable
Error
29
13
Field name
28
12
Reserved
TENTATIVE
27
11
TMPA900CM- 882
26
10
This bit is set by the HC when HCD sets the
OwnershipChangeRequest field in HcCommandStatus. This event,
when unmasked, will always generate an System Management
Interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is
not implemented.
This bit is set when the content of HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] is changed.
This bit is set when the MSb of HcFmNumber (bit 15) changes value
from 0 to 1 or from 1 to 0, and after HccaFrameNumber is updated.
This bit is set when the HC detects a system error not related to USB.
The HC should not proceed with any processing nor signaling before
the system error is corrected. HCD clears this bit after the HC is reset.
25
9
24
8
23
Reserved
7
RHSC
22
6
0
Address = (0xF450_0000) + (0x000C)
Function
FNO
21
5
0
20
UE
4
0
R/W
R/W
19
RD
3
0
18
SF
2
0
TMPA900CM
2009-10-14
WDH
17
1
0
SO
16
0
0