BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 301

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:16]
[15:13]
[12]
[11]
[10]
[9:7]
[6]
[5:3]
[2]
[1:0]
[Description]
Bit
a. <set_burst_align>
Note: This register cannot be written while it is in the Reset state.
4.
The APB registers smc_set_opmode act as holding registers. Executing either of the
following two makes the setting values to be effective:
For asynchronous transfers:
When set_rd_sync = 0, MPMC1 always aligns read bursts to the memory burst boundary.
When set_wr_sync = 0, MPMC1 always aligns write bursts to the memory burst boundary.
(1) The smc_direct_cmd Register indicates only a register update is taking place.
(2) The smc_direct_cmd Register indicates either a modereg operation or a memory
access has taken place, and is complete.
−
set_burst_align
set_bls
Reserved
-
set_wr_bl
set_wr_sync
set_rd_bl
set_rd_sync
set_mw
smc_set_opmode_5 (SMC Set Opmode Register)
Symbol
Bit
−
WO
WO
WO
−
WO
WO
WO
WO
WO
Type
TENTATIVE
TMPA900CM- 300
Undefined
−
−
−
Undefined
−
−
−
−
−
Reset
Value
Read as undefined. Write as zero.
Memory burst boundary split setting:
0y000 = bursts can cross any address boundary
0y001 = split at the 32-beat burst boundary
0y010 = split at the 64-beat burst boundary
0y011 = split at the 128-beat burst boundary
0y100 = split at the 256-beat burst boundary
other = Reserved
Byte Enable (SMCBE0-1) timing setting:
0y0 = SMCCSn timing
0y1 = SMCWEn timing
Read as undefined. Write as zero.
Read as undefined. Write as zero.
Write burst length
(holding register)
0y000 = 1-beat
0y001 = 4-beats
other = Reserved
Holding register of the wr_sync field set value:
0y0 = asynchronous write mode
0y1 = Reserved
Read burst length
0y000 = 1-beat
0y001 = 4-beats
other = Reserved
Holding register of the rd_sync field set value:
0y0 = asynchronous read mode
0y1 = Reserved
Holding register of the memory data bus width set value:
0y00 = reserved
0y01 = 16-bits
0y10 = 32-bits
0y11 = Reserved
Address = (0xF431_1000) + (0x0018)
Description
TMPA900CM
2009-10-14