BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 208
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 208 of 959
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3.10.3.1 DMC (Dynamic Memeory Controller)
Support memory
Data bus width
Access areas
Timing adjustment
Command
Clock
External control pin
(1) DMC function outline
Table 3.10.3 shows features of DMC.
SDR SDRAM
Support separate bus only
16 bit/ 32 bit data bus width
Max 512MB acess area
Chip select: DMCCSn only
Adjustable AC timing by register
Mode Register setting, Auto refresh, Self Refresh, Active, Precharge, Read/Write command,
Powerdown etc.
DMCSCLK frequency = f
Fixed to GND (Input clock pin DMCCLKIN can not be used)
D31 to D0, A23 to A0,
DMCSDQM3, DMCSDQM2, DMCSDQM1, DMCSDQM0,
DMCCSn, DMCWEn, DMCRASn, DMCCASn,
DMCBA0, DMCBA1, DMCCKE, DMCSCLK, DMCDCLKN, DMCAP
Table 3.10.3 Features of DMC
TENTATIVE
TMPA900CM- 207
HCLK
Features
TMPA900CM
2009-10-14
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