BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 273

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:4]
[3:1]
[0]
[Description]
Bit
a. <cas_latency>
b. <cas_half_cycle>
Note: Use dmc_cas_latency_5 to configure cas latency of memory controler,
6.
CAS latency setting (number of memory clocks): 0y000 to 0y111
CAS latency offset setting:
0y0 = 0 offset
0y1 = Half-cycle offset
The setting of cas latency(CL) is different from SDR_SDRAM.
The CL setting value of memory controler is 1 smaller than the CL setting value of DDR_SDRAM memory.
Example:
dmc_cas_latency_5 ← 0x00000004 (set memory controller CL = 2)
dmc_direct_cmd_5 ← 0x00080033
dmc_cas_latency_5 (DMC CAS Latency Register)
−
cas_latency
cas_half_cycle
Symbol
Bit
−
R/W
R/W
Type
TENTATIVE
TMPA900CM- 272
(set DDR SDRAM memory CL = 3)
Undefined
0y11
0y0
Reset
Value
Read as undefined. Write as zero.
CAS latency setting (number of memory clocks)
0y000 to 0y111
set CAS latency offset
0y0 = 0 offset
0y1 = Half cycle offset
Address = (0xF431_0000) + (0x0014)
Description
TMPA900CM
2009-10-14