BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 412

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

38. UART0DMACR (UART0 DMA control register)
39. UART2DMACR (UART2 DMA control register)
[31:3]
[2]
[1]
[0]
[31:3]
[2]
[1]
[0]
[Description]
a. <DMAONERR>
Bit
Bit
Note1: For example, if 19 characters have to be received and the watermark level is programmed to be four, then the
Note2: The bus width must be set to 8-bits, if you transfer the data of tranmit/ receive FIFO by using DMAC.
When this bit is set to 1, the DMA receive request output, UARTxRXDMASREQ or
UARTxRXDMABREQ, is disabled on assertion of a UART error interrupt.
DMA controller transfers four bursts of four characters and three single transfers to complete the stream.
−
DMAONERR
TXDMAE
RXDMAE
−
DMAONERR
TXDMAE
RXDMAE
Symbol
Symbol
Bit
Bit
−
R/W
R/W
R/W
−
R/W
R/W
R/W
Type
Type
TENTATIVE
TMPA900CM- 411
−
0y0
0y0
0y0
−
0y0
0y0
0y0
Reset
Reset
Value
Value
Read as undefined. Write as zero.
DMA on error
0y1: Available
0y0: Not available
Transmit FIFO DMA enable
0y0: Disable
0y1: Enable
Receive FFO DMA enable
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
DMA on error
0y1: Available
0y0: Not available
Transmit FIFO DMA enable
0y0: Disable
0y1: Enable
Receive FFO DMA enable
0y0: Disable
0y1: Enable
Address = (0xF200_0000) + (0x0048)
Address = (0xF200_4000) + (0x0048)
Description
Description
TMPA900CM
2009-10-14