BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 496

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
[Description]
int_nak
int_ep
int_ep0
int_sof
int_rx_zero
int_status
int_status_nak
int_setup
a. <int_mw_rerror>
b. <int_dmac_reg_rd>
c.
d. <int_mr_ahberr>
Will be set to 1 when the access to the endpoint has started Master Write transfer during
the setting of common bus access (bus_sel bit of EPx_Status register is 0).
0y0: Not detected
0y1: Endpoint read error occurred in Master Write
Will be set to 1 when the register access executed by the setting of DMAC Read Request
register is completed and the value read to DMAC Read Value register is set.
0y0: Not detected
0y1: Register read completed
<int_udc2_reg_rd>
Will be set to 1 when the UDC2 access executed by the setting of UDC2 Read Request
register is completed and the value read to UDC2 Read Value register is set.
Also set to 1 when Write access to the internal register of UDC2 is completed.
0y0: Not detected
0y1: Register read/write completed
This status will be set to 1 when the AHB error has occurred during the operation of
Master Read transfer.
After this interrupt has occurred, the Master Read transfer block needs to be reset by the
mr_reset bit of DMAC Setting register.
0y0: Not detected
0y1: AHB error occurred
Symbol
Bit
RO
RO
RO
RO
RO
RO
RO
RO
Type
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
TENTATIVE
Reset
Value
TMPA900CM- 495
UDC2_INT_NAK register
UDC2 INT_EP register
UDC2 INT_EP0 register
UDC2 INT_SOF register
UDC2 INT_RXDATA0 register
UDC2 INT_STATUS register
UDC2 INT_STATUS_NAK register
UDC2 INT_STATUS register
Description
TMPA900CM
2009-10-14