BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 661
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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[31:4]
[3]
[2]
[1]
[0]
[Description]
Bit
a. <I2SRx_OVERFLOW_INT>, <I2SRx_UNDERFLOW_INT>, <I2STx_OVERFLOW_INT>,
18. I2SINT (I
<I2STx_UNDERFLOW_INT>
This register indicates the interrupt status of each interrupt source. To monitor the FIFO
error status by using each interrupt source, the corresponding bit of the interrupt mask
register (I2SINTMSK) must be cleared.
When an interrupt is generated from one of these sources, the interrupt controller
generates an I2SINT interrupt. The interrupt source can be identified by monitoring each
interrupt source bit of the I2SINT register.
Each bit of this register is cleared to 0 by writing 1.
−
I2SRx_OVERFLOW_INT
I2SRx_UNDERFLOW_INT
I2STx_OVERFLOW_INT
I2STx_UNDERFLOW_INT
Bit Symbol
2
S Interrupt Register)
TENTATIVE
TMPA900CM- 660
−
R/W
R/W
R/W
R/W
Type
Undefined
0y0
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
Rx FIFO overflow interrupt:
0y0: No interrupt
0y1: Interrupt generated
Rx FIFO underflow interrupt:
0y0: No interrupt
0y1: Interrupt generated
Tx FIFO overflow interrupt:
0y0: No interrupt
0y1: Interrupt generated
Tx FIFO underflow interrupt:
0y0: No interrupt
0y1: Interrupt generated
Address = (0xF204_0000) + (0x0050)
Description
TMPA900CM
2009-10-14
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