BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 444

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<Serial transfer rate>
<Prescaler clock width (= noise cancellation width)>
and I2C0PRS<PRSCK[4:0]>. The prescaler clock which is divided according to
I2C0PRS<PRSCK[4:0]> is used as the reference clock for generating the serial clock. The
prescaler clock is further divided according to I2C0CR1<SCK[2:0]> and used as the serial
clock. The default setting of the prescaler clock is “divide by 1 (＝ PCLK)”.
Note:
Note:
0
0
0
0
1
1
1
1
<PRSCK[4:0]>, p = 1-32) and serial clock setting value “n” (2C0CR1<SCK[2:0]>, n = 0-7)
based on the operating frequency (PCLK) as follows:
Writes to these bits must be done before a start condition is generated or after a stop condition is generated.
Writes during transfer will cause unexpected operation.
prescaler setting value “p” (I2C0PRS<PRSCK[4:0]>, p = 1-32) based on the operating
frequency (PCLK) as follows:
The serial clock rate to be output from the master is set through I2C0CR1<SCK[2:0]>
The serial clock rate may not be constant due to the clock synchronization function.
SCK[2:0] = (n)
The serial clock rate (Fscl) is determined by prescaler setting value “p” (I2C0PRS
The prescaler clock width (Tprsck) (= noise cancellation width) is determined by
(= Noise cancellation width)
50 ns < Prescaler clock width Tprsck (ns) ≤ 150ns
Prescaler clock width Tprsck (ns)
Serial clock rate Fscl (kHz) ＝
Setting the prescaler clock width out of this range is prohibited in both master and slave modes.
frequency (PCLK) and must satisfy the following condition:
The allowed range of prescaler setting value “p” (I2C0PRS<PRSCK[4:0]>) varies depending on the operating
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0y00001 (divide by 1)
TENTATIVE
TMPA900CM- 443
144
272
528
20
24
32
48
80
＝
0y01101 (divide by 13)
PRSCK [4:0] = (p)
p ×( 2
(Ratio to PCLK)
PCLK(MHz)
1040
1872
3536
6864
260
312
416
624
n
PCLK (MHz)
＋
2
＋16 )
1
× 1000
0y00000 (divide by 32)
× 1000 × p
16896
1024
1536
2560
4608
8704
640
768
TMPA900CM
2009-10-14