BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 690

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:5]
[4]
[3]
[2]
[1]
[0]
[31:5]
[4]
[3]
[2]
[1]
[0]
Bit
Bit
10. LCDMIS (Masked Interrupt Status Register)
11. LCDICR (Interrupt Clear Register)
LCDRIS register and the LCDIMSC (Enable) register. The logical ORs of all interrupts are
given to the system interrupt controller.
LCDMIS is a read-only register. This register serves as the logical AND for each bit of the
−
MBERRORINTR
VCOMPINTR
LNBUINTR
FUFINTR
−
−
Clear
MBERROR
Clear Vcomp
Clear LNBU
Clear FUF
−
Symbol
Symbol
Bit
Bit
Type
−
RO
RO
RO
RO
−
Type
−
WO
WO
WO
WO
−
Undefined
0y0
0y0
0y0
0y0
Undefined
Undefined
0y0
0y0
0y0
0y0
Undefined
Reset
Value
TENTATIVE
TMPA900CM- 689
Reset
Value
Read undefined. Write as zero.
Clears AMBA AHB master bus error interrupt request flags
0y0: No change
0y1: Clear
Clears vertical sync. interrupt request flags.
0y0: No change
0y1: Clear
Clears LCD next address base update interrupt request flags.
0y0: No change
0y1: Clear
Clears FIFO underflow interrupt request flags.
0y0: No change
0y1: Clear
Read undefined. Write as zero.
Read as undefined. Write as zero.
AMBA AHB master bus error status bit
0y0: Clear
0y1: Interrupt requested
Vertical sync. interrupt status bit
0y0: Clear
0y1: Interrupt requested
LCD next address base update status bit
0y0: Clear
0y1: Interrupt requested
FIFO underflow status bit
0y0: Clear
0y1: Interrupt requested
Read as undefined.
Address = (0xF420_0000) + (0x0024)
Description
Description
Address = (0xF420_0000) + (0x0028)
TMPA900CM
2009-10-14