BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 4

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1.
Overview and Features
(1) ARM926EJ-S manufactured by ARM is used.
(2) Maximum operating frequency: 200 MHz(@0∼70°C) / 150MHz(@-20∼85°C)
(3) A 7-layer multi bus system is used.
(4) Memory access
(5) Memory controller
(6) 16-bit timer
(7) Synchronous serial bus interface: 2 channels
(8) I
TMPA900CM is a 32-bit RISC microcontroller with a built-in ARM9
TMPA90xCMXBG is a 289-pin BGA package product.
Features of the product are as follows:
Supports SPI mode / Microwire mode
2
C bus interface: 2 channels
(Double Data Rate) LVCMOS_I/O type SDRAM can be supported (SSTL_IO type DDR
SDRAM cannot be supported).
Data cache: 16 Kbytes
Instruction cache: 16 Kbytes
Bus Master1: CPU data
Bus Master2: CPU instruction
Bus Master3: LCD controller
Bus Master4: LCD data process accelerator
Bus Master5: DMA controller 1
Bus Master6: DMA controller 2
Bus Master7: USB device controller
Built-in RAM: 32 Kbytes (can be used as program, data, and display memory)
Built-in ROM: 16 Kbytes (boot memory)
4 GB linear access space (effective space: approximately 1.7 GB)
Separate bus system:
Chip-select output: 2 channels
Chip-select exclusive for DRAM: 1 channel
Depending on the external pin selection, SDR (Single Data Rate)-type SDRAM and DDR
Support Asynchronous Static Memory, but Not support synchronous Static Memory.
6 channels 16-bit timers including 2 channel timers with PWM function.
It can be loaded to the built-in RAM from USB
External address
External data bus
32-Bit RISC Microcontroller
TMPA900CMXBG
TENTATIVE
TMPA900CM- 3
24 bits: A0-A23
32bit:D0-D31
(Only a 16-bit bus is available for Mobile DDR SDRAM)
TM
cpu core.
TMPA900CM
2009-10-14

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