BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 381

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. UART2SR/ UART2ECR (UART2 Receive status register/ UART2 error clear register)
[31:4]
[3]
[2]
[1]
[0]
[31:0]
[Description]
a. <OE>
b. <BE>
Bit
Bit
Note 1: The UARTxSR/UARTxECR register is the receive status register/error clear register. Receive status can also
Note 2: The receive data must be read first from UARTxDR before the error status associated with that data is read
This bit is set to 1 if data is received and the FIFO is already full. In this case, the received
data is not stored in the FIFO and is discarded.
The bit is cleared to 0 once an empty space is made in the FIFO and new data can be
written to it.
This bit is set to 1 if a break condition was detected, indicating that the receive data input
(defined as start, data parity, and stop bits) was held Low for longer than a full-word
transmission time.
be read from UARTxSR. If the status is read from this register, the status information for break, framing and
parity corresponds to the data read from UARTxDR prior to reading UARTxSR. The status information for
overrun is set immediately when an overrun condition occurs. A write to UARTxECR clears the framing, parity,
break and overrun errors. All the bits are cleared to 0 on reset.
from UARTxSR. This read sequence cannot be reversed because the status register UARTxSR is updated
only when the data is read from the data register UARTxDR. The status information can also be read directly
from the UARTxDR register.
−
OE
BE
PE
FE
−
Symbol
Symbol
Bit
Bit
−
RO
RO
RO
RO
WO
Type
Type
TENTATIVE
TMPA900CM- 380
−
0y0
0y0
0y0
0y0
−
Reset
Reset
Value
Value
Read as undefined.
Overrun error:
0y0: There is an empty space in the FIFO.
0y1: Overrun error flag
Break error
0y0: No error detected
0y1: Error detected
Parity error
0y0: No error detected
0y1: Error detected
Framing error
0y0: No error detected
0y1: Error detected
A write to this register clears framing, parity,
break, and overrun errors. The data value has
no significance.
The address of this register is the same as that
of the UART1SR register.
Address = (0xF200_4000) + (0x0004)
Address = (0xF200_4000) + (0x0004)
Description
Description
TMPA900CM
2009-10-14